In the conventional self aligned silicides fabrication, which is has been given the name "salicide process", the silicidation process usually is carried out after the formation of the junctions. In the case of NMOS, PMOS, CMOS and BiCMOS, the silicidation process is after the source/drain implant and anneal and, in the case of bipolar, the silicidation process is after the emitter to base junction formation and anneal. For example, in the conventional CMOS fabrication process, after the gate definition, LDD implant, spacer formation and source/drain implant screen oxide, the source and drains are implanted and annealed. After removal of the screen oxide and a clean step, titanium or another refractory metal or Group VIII metals is deposited and annealed to form the silicide, such as titanium silicide. During the silicidation process with titanium, the silicon is the moving species and, as the silicide is formed, the silicon below the original silicon surface is consumed. It is well established that 1 angstrom of titanium (Ti) will react with 2.27 angstroms of crystalline silicon to produce 2.4 angstroms of titanium silicide (TiSi.sub.2).
Advanced high performance submicron NMOS, PMOS, CMOS, biCMOS and bipolar integrated circuits require further down scaling of the devices in the lateral and vertical directions. However, as the gate length is scaled down, the vertical dimension of the devices, such as gate oxide thickness and junction depth need to be scaled down accordingly for optimum performance of the devices and to alleviate short channel effects. However, as vertical and laterally scaling of these devices continues, the fabrication of very shallow junctions create additional challenges due to the very low implant energy required to fabricate very shallow junctions and the higher parasitic source and drain resistance for field effect transistors (FETs), such as CMOS, and emitter resistance for bipolar introduced by the shallow junctions, as well as excessive off leakage current for FETs. To reduce the parasitic resistances, these advanced integrated circuits employ silicides at the shallow junctions and thereby increase device speed and performance. However, a major portion (.about.one-half) of the originally implanted shallow junction in the silicon substrate is consumed by the silicidation in the conventional salicidation process and such consumption of the silicon substrate during silicidation degrades the integrity of the shallow junctions and sets a lower limit for the junction depth. A similar situation exists in using the conventional method in fabricating silicided shallow emitters in bipolar or biCMOS integrated circuits. In addition, the junction depths of the silicided sources and drains or the junction depth of the silicided emitters are all the same depth and have common device characteristics.